In the past few decades, in order to achieve higher chip densities, faster work speeds and lower power consumption, a feature size of a conventional metal-oxide-semiconductor field effect transistor (MOSFET) has continuously been scaling down, and currently it is entering into a nanoscale regime. However, a resultant severe challenge is a short channel effect, such as a threshold voltage roll-off (Vt roll-off), a drain induced barrier lowering (DIBL) or a source and drain punch-through, which cause significant increase of the off-state leakage current and thus deteriorate device performance.
Currently, various improvements and structures have been introduced to minimize a negative influence of the short channel effects, among which a tunneling field effect transistor (TFET) is a promising candidate. Since when the MOSFET device is in a sub-threshold state, i.e., the device is operating in weak inversion, and at this situation thermionic emission is a major transport mechanism, thus a sub-threshold slope of the MOSFET device at room temperature is limited to 60 mV/dec. Compared with the conventional MOSFETs, since an active region of the TFET device is essentially a tunneling junction, the TFET has a weaker or no short channel effect; moreover, a major current transport mechanism of the TFET is a band-to-band tunneling, a drain current in a sub-threshold region increase exponentially with an applied gate-source voltage, and therefore the TFET has a lower sub-threshold slope and the drain current is almost not influenced by operating temperature.
A fabricating process of the TFET is compatible with that of a conventional complementary metal-oxide-semiconductor field effect transistor (CMOSFET). A structure of the TFET is based on a MOS-gated p-i-n diode. A typical conventional n-type TFET is shown in FIG. 1. Specifically, the n-type TFET comprises a source region 1000′ with p-type doping and a drain region 2000′ with n-type doping, a channel region 3000′ separates the source region 1000′ and the drain region 2000′, and a gate stack 4000′ comprises a gate dielectric layer and a gate electrode, which are disposed above the channel region 3000′.
When the TFET device is in an off-state, i.e., when no gate voltage is applied, a junction formed between the source region 1000′ and the drain region 2000′ is a reverse biased diode. Since a potential barrier established by the reverse biased diode is larger than that established by the CMOSFET, even when a channel length is very short, the direct tunneling current and the sub-threshold leakage current of the TFET device decrease greatly. When a voltage is applied to the gate terminal of the TFET, an electron conducting path is generated in the channel region 3000′ by the field effect. Once an electron density in the channel becomes degenerated, a tunneling junction is formed between the source region 1000′ and the channel region 3000′. Then the tunneling current flows through this tunneling junction. From a viewpoint of the energy band, a tunnel length of a p-n junction formed between the source region 1000′ and the channel region 3000′ is mainly adjusted by controlling the gate voltage for the TFET device based on a MOS-gated p-i-n diode. With a geometric dimension of the TFET shrinking down, in order to obtain a higher ratio of on-state current to off-state current (Ion/Ioff) and a lower sub-threshold slope, typical methods used are: improving a steepness of a impurity doping concentration at an interface of the p-n junction formed between the source region and the channel region; introducing a narrow energy band gap material as the source region so that a hetero-structure is formed between the source region and the channel region. For example, silicon is used for the channel while germanium (Ge) or InAs etc. is employed for the source region. However, these methods greatly increase difficulty and cost of the fabrication process. The introduction of the narrow energy band gap materials inevitably results in a sharp increase of the off-state current as well.